Samsung patents memory chips that self-adjust clock timing
This patent describes a storage device where memory chips monitor their own clock signals to detect timing imbalances. A dedicated circuit compares these signals and sends feedback to each chip so they can adjust their internal clock cycles for better accuracy.
In the filing’s own words
A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
What exactly they claim (claim 1)
1. A memory device comprising: a clock pin; a plurality of memories connected to the clock pin; and a plurality of input/output pins commonly connected to the plurality of memories, wherein the memory device is configured to: receive a chip enable command through the plurality of input/output pins in a first period of a chip enable period; receive an address for the plurality of memories through the plurality of input/output pins in a second period of the chip enable period; receive a duty correction circuit (DCC) command through the plurality of input/output pins in a first period of a DCC training period; receive an address for the plurality of memories through the plurality of input/output pins in a second period of the DCC training period; and receive a clock signal through the clock pin in a third period of the DCC training period, and wherein the plurality of memories is configured to perform duty correction operations on a plurality of internal clock signals generated based on the clock signal during the third period of the DCC training period.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device
- Patent number
- US12755768B2
- Application number
- 18781289
- Filed
- Jul 23, 2024
- Granted
- Oct 6, 2026
- Inventors
- 6
- Claims
- 20
Classified under
G11C 7/222 Physics & computingG06F 1/04 Physics & computingG06F 3/0604 Physics & computingG06F 3/0659 Physics & computingG06F 3/0673 Physics & computingG11C 29/023 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.