Samsung patents memory circuit design to speed up data reading
This patent describes a specific layout for a sense amplifier, a tiny circuit that reads data from memory chips. It uses a unique arrangement of transistors to make the electrical path to one side of the memory cell faster than the other, allowing the chip to distinguish between a 0 and a 1 more quickly.
In the filing’s own words
A sense amplifier connected to a bit line and a complementary bit line, the sense amplifier including a first transistor connected between the bit line and a first node and including a first gate terminal connected to a third node, a second transistor connected between the first node and the complementary bit line and including a second gate terminal connected to a fourth node, third transistor connected between the bit line and a second node and including a third gate terminal connected to the third node, and a fourth transistor connected between the complementary bit line and the second node and including a fourth gate terminal connected to the fourth node, wherein first and second RC values viewed from the sense amplifier toward the bit line and the complementary bit line differ, and wherein the second transistor is configured to receive a program voltage during a first time period.
What exactly they claim (claim 1)
1. A sense amplifier connected to a bit line and a complementary bit line, comprising: a first transistor connected between the bit line and a first node, the first transistor including a first gate terminal connected to a third node; a second transistor connected between the first node and the complementary bit line, the second transistor including a second gate terminal connected to a fourth node; a third transistor connected between the bit line and a second node, the third transistor including a third gate terminal connected to the third node; a fourth transistor connected between the complementary bit line and the second node, the fourth transistor including a fourth gate terminal connected to the fourth node; and a protection transistor connected between the third node and the complementary bit line, wherein a first resistance-capacitance (RC) value as viewed from the sense amplifier toward the bit line is smaller than a second RC value as viewed from the sense amplifier toward the complementary bit line, wherein the second transistor is configured to receive a program voltage that is higher than a power supply voltage during a first time period, and wherein the protection transistor is turned off during the first time period.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Sense amplifiers and operation methods thereof, and memory devices including the same
- Patent number
- US12755764B2
- Application number
- 18633650
- Filed
- Apr 12, 2024
- Granted
- Oct 6, 2026
- Inventors
- 2
- Claims
- 16
Classified under
G11C 7/062 Physics & computingG11C 7/065 Physics & computingG11C 7/08 Physics & computingG11C 7/12 Physics & computingG11C 11/4091 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.