Samsung patents chip design that processes AI data one bit at a time
This patent describes a specific layout for a computer chip designed to run deep neural networks, a type of software used in AI. It uses a method called bit-serial computation, where data is processed one bit at a time in a sequence, rather than all at once, to handle the math efficiently.
In the filing’s own words
A system for bit-serial computation in a neural network is described. The system may be embodied on an integrated circuit and include one or more bit-serial tiles for performing bit-serial computations in which each bit-serial tile receives input neurons and synapses, and communicates output neurons. Also included is an activation memory for storing the neurons and a dispatcher. The dispatcher reads neurons and synapses from memory and communicates either the neurons or the synapses bit-serially to the one or more bit-serial tiles. The other of the neurons or the synapses are communicated bit-parallelly to the one or more bit-serial tiles, or according to a further embodiment, may also be communicated bit-serially to the one or more bit-serial tiles.
What exactly they claim (claim 1)
1. A system for bit-serial computation in a neural network, comprising: one or more bit-serial tiles for performing bit-serial computations in a neural network wherein each bit-serial tile processes two or more windows in parallel, each bit-serial tile receiving input neurons in two or more windows and synapses in two or more filters, and generating output neurons; and an activation memory for storing neurons and in communication with the one or more bit-serial tiles using a dispatcher, wherein the dispatcher reads neurons from the activation memory and communicates the neurons to the one or more bit-serial tiles via two or more window lanes for each bit-serial tile, wherein the dispatcher reads synapses from a synapse buffer and communicates the synapses to the one or more bit-serial tiles via two or more filter lanes for each bit-serial tile, and wherein one of the neurons or the synapses are communicated to the one or more bit-serial tiles bit-serially and the other of the neurons or the synapses are communicated to the one or more bit-serial tiles bit-parallelly.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Accelerator for deep neural networks
- Patent number
- US12755139B2
- Application number
- 18108292
- Filed
- Feb 10, 2023
- Granted
- Oct 6, 2026
- Inventors
- 5
- Claims
- 20
Classified under
G06N 3/063 Physics & computingG06N 3/049 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.