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Samsung patents chip package design with raised walls to improve reliability

Samsung has been granted a patent for a semiconductor package design that includes a raised wall, or dam, on the base substrate. This structure sits between two different types of chip connections to help manage material flow during manufacturing. The filing describes how this layout, combined with a nearby recessed trench, aims to increase the yield and reliability of the final device.

Why it mattersThis is a routine improvement in chip packaging that helps manufacturers produce more working chips, but it does not introduce a new consumer-facing feature.

In the filing’s own words

A semiconductor package includes a substrate, a first semiconductor chip on an upper surface of the substrate, and electrically conductive bumps extending between and electrically connected to the substrate and the first semiconductor chip. A non-conductive film layer is provided, which has at least a portion extending between the electrically conductive bumps. A second semiconductor chip is provided, which extends on the upper surface of the substrate. Electrically conductive wires are provided that electrically connect respective portions of the second semiconductor chip to respective portions of the upper surface of the substrate. In addition, the upper surface of the substrate includes a dam, which protrudes between one of: (i) a region overlapping the second semiconductor chip, and (ii) a region connected to the wires and a region overlapping the first semiconductor chip. The upper surface of the substrate may also include a trench recessed alongside at least a portion of the dam.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a substrate; a first semiconductor chip on an upper surface of the substrate; electrically conductive bumps extending between and electrically connected to the substrate and the first semiconductor chip; a non-conductive film layer having at least a portion extending between the electrically conductive bumps; a second semiconductor chip extending on the upper surface of the substrate; and electrically conductive wires that electrically connect respective portions of the second semiconductor chip to respective portions of the upper surface of the substrate; wherein the upper surface of the substrate includes a dam, which protrudes between one of: (i) a region overlapping the second semiconductor chip, and (ii) a region connected to the wires and a region overlapping the first semiconductor chip; wherein the upper surface of the substrate further includes a trench recessed alongside at least a portion of the dam; wherein the second semiconductor chip is attached to the upper surface of the substrate, wherein at least a portion of the dam and at least a portion of the trench overlap a space between the first and second semiconductor chips, and wherein a distance between the dam and the second semiconductor chip is less than a distance between the dam and the first semiconductor chip.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Packaged integrated circuit devices with enhanced dam structures that provide increased yield and reliability
Patent number
US12751338B2
Application number
18475530
Filed
Sep 27, 2023
Granted
Sep 29, 2026
Inventors
1
Claims
19

Classified under

H10W 90/00 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 72/387 Electricity & electronicsH10W 74/15 Electricity & electronicsH10W 90/24 Electricity & electronicsH10W 90/724 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.