Samsung patents chip design with edge patterns to protect connections
This patent describes a semiconductor chip layout where a specific pattern is placed along the edges of the chip's base. The design includes a vertical wire that connects the top of the chip to the bottom, with a protective line structure positioned next to the connection point on the underside.
In the filing’s own words
A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first semiconductor chip, the first semiconductor chip comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a dam structure including a line pattern extending lengthwise horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode, wherein the first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor chip, semiconductor device, and semiconductor package including the same
- Patent number
- US12751331B2
- Application number
- 18370283
- Filed
- Sep 19, 2023
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 72/387 Electricity & electronicsH10W 74/15 Electricity & electronicsH10W 80/721 Electricity & electronicsH10W 90/297 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.