Samsung patents stacked chip design with wider top layer
Samsung has been granted a patent for a semiconductor package that stacks two chips vertically to save space. The design features a wider top chip sitting on a smaller bottom chip, connected by metal posts and pads to improve how the components link together.
In the filing’s own words
Disclosed is a semiconductor package including a substrate, a first semiconductor chip on the substrate and including a through via in the first semiconductor chip and a plurality of first bonding pads on an upper portion of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a plurality of second bonding pads on a lower portion of the second semiconductor chip, and a conductive post between a top surface of the substrate and a bottom surface of the second semiconductor chip and laterally spaced apart from the first semiconductor chip. The first bonding pads are in contact with the second bonding pads. A width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a substrate; a first semiconductor chip on the substrate, wherein the first semiconductor chip includes a through via in the first semiconductor chip and a plurality of first bonding pads on an upper portion of the first semiconductor chip; a second semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip includes a plurality of second bonding pads on a lower portion of the second semiconductor chip; a conductive post between a top surface of the substrate and a bottom surface of the second semiconductor chip and laterally spaced apart from the first semiconductor chip; and a bump structure below the first semiconductor chip where the bottom surface of the substrate provides a base reference plane, wherein the bump structure includes: a bump pad below the conductive post and below the through via where the bottom surface of the substrate provides the base reference plane; a barrier pattern in contact with a bottom surface of the bump pad; and a bonding pattern and a solder bump that are sequentially provided in a downward direction below the barrier pattern where the bottom surface of the substrate provides the base reference plane, wherein the first bonding pads are in contact with the second bonding pads, and wherein a width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package
- Patent number
- US12751330B2
- Application number
- 18356325
- Filed
- Jul 21, 2023
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 16
Classified under
H10W 90/00 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 70/69 Electricity & electronicsH10W 74/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.