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SamsungGranted patentChips & hardwareInterest 3/10

Samsung patents chip package design with stacked components

Samsung describes a method for building a semiconductor package where multiple smaller chips are stacked next to a main chip on a base board. The design uses a protective sealant to fill gaps and holes in the board, with a film attached to the bottom to cover the exposed material.

Why it mattersThis is a specific manufacturing technique that could help make computer chips more compact and secure, though it is a detailed engineering update rather than a new consumer feature.

In the filing’s own words

A semiconductor package includes a package substrate extending in a first direction, the package substrate having at least one first opening in a chip mounting region of the package substrate; a first semiconductor chip mounted in the chip mounting region on an upper surface of the package substrate; a plurality of second semiconductor chips sequentially stacked on the upper surface of the package substrate and spaced apart from the first semiconductor chip in the first direction; a sealant covering the first semiconductor chip and the plurality of second semiconductor chips on the package substrate, the sealant filling a gap between the first semiconductor chip and the package substrate and filling an interior of the at least one first opening of the package substrate; and a taping film attached on a lower surface of the package substrate to cover at least a portion of the sealant exposed in the first opening.

What exactly they claim (claim 1)

1. A semiconductor package, comprising: a package substrate, the package substrate having a first opening in a chip mounting region of the package substrate; a first semiconductor chip mounted in the chip mounting region on an upper surface of the package substrate; a plurality of second semiconductor chips sequentially stacked on the upper surface of the package substrate and spaced apart from the first semiconductor chip in a first horizontal direction; a sealant covering the first semiconductor chip and the plurality of second semiconductor chips on the package substrate, the sealant filling a gap between the first semiconductor chip and the package substrate and filling an interior of the first opening of the package substrate; and a taping film attached on a lower surface of the package substrate to cover at least a portion of the sealant exposed in the first opening.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor package and method of manufacturing the semiconductor package
Patent number
US12751315B2
Application number
18618160
Filed
Mar 27, 2024
Granted
Sep 29, 2026
Inventors
1
Claims
20

Classified under

H10W 74/114 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 74/01 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 72/865 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.