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Samsung patents chip package design that shrinks connection points

Samsung has been granted a patent for a semiconductor package that uses a specific arrangement of metal posts and solder balls to connect a chip to its base. The design places a thin metal post inside a recessed area to create a direct electrical link, aiming to make the overall package smaller while maintaining high capacity.

Why it mattersThis is a routine improvement in chip packaging that helps manufacturers fit more components into smaller spaces, which is standard practice for advancing processor technology.

In the filing’s own words

A semiconductor package includes a substrate including a first wiring pattern, a redistribution layer disposed on an upper surface of the substrate, a solder resist layer disposed on an upper surface of the redistribution layer and including a second recess formed inside the solder resist layer, a first conductive terminal disposed on sidewalls and a bottom surface of the second recess, a first solder ball disposed on the first conductive terminal, and a semiconductor chip disposed on the solder resist layer and electrically directly connected to the redistribution layer through the first solder ball. The redistribution layer includes a first wiring pad, a first recess formed on an upper surface of the first wiring pad, a first metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a first wiring post at least partially disposed on the first metal seed layer inside the first recess.

What exactly they claim (claim 1)

1. A semiconductor package, comprising: a substrate including a first wiring pattern; a first redistribution layer disposed on an upper surface of the substrate in a vertical direction, wherein the first redistribution layer includes a first wiring pad, a first recess formed on an upper surface of the first wiring pad, a first metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a first wiring post at least partially disposed on the first metal seed layer inside the first recess, wherein a width of the first wiring post is smaller than a width of the first recess in a horizontal direction, wherein a width of an entire body of the first wiring post is uniform along the vertical direction and a height of the first wiring post extends above the first wiring pad, wherein a bottom surface of the first metal seed layer contacts the first wiring pad; a first solder resist layer disposed on an upper surface of the first redistribution layer and including a second recess formed inside the first solder resist layer; a first conductive terminal disposed on sidewalls and a bottom surface of the second recess; a first solder ball disposed on the first conductive terminal; and a first semiconductor chip disposed on the first solder resist layer and electrically connected to the first redistribution layer through the first solder ball.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Miniaturized high-capacity semiconductor package
Patent number
US12751301B2
Application number
17806985
Filed
Jun 15, 2022
Granted
Sep 29, 2026
Inventors
1
Claims
16

Classified under

H10W 70/65 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/401 Electricity & electronicsH10W 72/072 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.