Samsung patents chip packaging design with overlapping signal lines
This filing describes a specific layout for semiconductor packages, which are the protective housings for computer chips. It details how signal lines on the base substrate are arranged to intersect with connection points, creating a structured path for data to move between the chip and the outside world.
In the filing’s own words
The present disclosure relates to semiconductor packages. An example semiconductor package comprises a package substrate that includes a signal pad and a ground pad, an interposer substrate on the package substrate, a semiconductor chip on the interposer substrate, a plurality of signal lines on a top surface of the package substrate, and a first connection terminal between the package substrate and the interposer substrate. Each signal line of the plurality of signal lines extends in a first direction. The plurality of signal lines and the signal pad are spaced apart in a second direction that intersects the first direction. The plurality of signal lines, the signal pad, and the ground pad are in contact with the top surface of the package substrate. The first connection terminal overlaps at least a portion of the plurality of signal lines in a plan view.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a package substrate that includes a signal pad and a ground pad; an interposer substrate on the package substrate; a semiconductor chip on the interposer substrate; a plurality of signal lines on a top surface of the package substrate; and a first connection terminal between the package substrate and the interposer substrate, wherein each signal line of the plurality of signal lines extends in a first direction, wherein the plurality of signal lines and the signal pad are spaced apart in a second direction that intersects the first direction, wherein the plurality of signal lines, the signal pad, and the ground pad are in contact with the top surface of the package substrate, and wherein the first connection terminal overlaps at least a portion of the plurality of signal lines in a plan view.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package
- Patent number
- US12751300B2
- Application number
- 18615675
- Filed
- Mar 25, 2024
- Granted
- Sep 29, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 70/635 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/724 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.