Samsung patents chip design that stacks memory layers for better density
Samsung describes a semiconductor device where a second layer of stacked components sits directly on top of a first layer containing circuit elements. The design uses vertical contact plugs to connect the layers and forms capacitors using the stacked gate electrodes and insulating materials. This structure allows for more compact integration of memory and logic components within the chip.
In the filing’s own words
A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure connected to the circuit elements, and a peripheral region insulating layer covering the circuit elements; and a second semiconductor structure including a second substrate on the first substrate, a first stack structure including first and second gate electrodes spaced apart from each other and stacked on the second substrate, interlayer insulating layers alternately stacked with the first and second gate electrodes, first and second contact plugs passing through the first and second gate electrodes, and contact plug insulating layers alternately disposed with the interlayer insulating layers and surrounding the contact plugs. The second semiconductor structure includes a first capacitor structure including the first gate electrode, a contact plug insulating layer(s), and the second contact plug, or the second gate electrode, a contact plug insulating layer(s), and the first contact plug.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first semiconductor structure including a substrate, circuit elements on the substrate, a lower interconnection structure including a first lower interconnection structure and a second lower interconnection structure electrically connected to the circuit elements, the first lower interconnection structure and the second lower interconnection structure having different electric potentials, and a peripheral region insulating layer on the circuit elements; and a second semiconductor structure including gate electrodes including a first gate electrode and a second gate electrode spaced apart from each other and stacked on a substrate of the second semiconductor structure in a first direction, the first gate electrode and the second gate electrode having different electric potentials, interlayer insulating layers alternately stacked with the gate electrodes, contact plugs including a first contact plug and a second contact plug passing through the gate electrodes and extending into the first semiconductor structure in the first direction, the first contact plug and the second contact plug having different electric potentials, and contact plug insulating layers alternately disposed with the interlayer insulating layers, the contact plug insulating layers extending around the contact plugs, wherein the second semiconductor structure further includes: a first capacitor structure including the first gate electrode, at least one of the contact plug insulating layers, and the second contact plug, or including the second gate electrode, at least one of the contact plug insulating layers, and the first contact plug; and a second capacitor structure including the first gate electrode, at least one of the interlayer insulating layers, and the second gate electrode, and wherein the first semiconductor structure further includes: a third capacitor structure including the first lower interconnection structure, the peripheral region insulating layer, and the second lower interconnection structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device and electronic system including semiconductor device
- Patent number
- US12751279B2
- Application number
- 18466289
- Filed
- Sep 13, 2023
- Granted
- Sep 29, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 43/35 Electricity & electronicsH10B 43/40 Electricity & electronicsH10D 84/813 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.