Samsung patents chip design with stepped edge to protect internal wiring
Samsung has been granted a patent for a semiconductor chip that features a specific stepped shape on the side of its protective coating. This design aligns with a test pattern on the chip's edge, creating a deeper groove that helps shield the internal connection points from damage during manufacturing or use.
In the filing’s own words
Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.
What exactly they claim (claim 1)
1. A semiconductor chip, comprising: a substrate including a device region and an edge region; a device layer and a wiring layer sequentially stacked on the substrate; a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate; an upper dielectric stack covering the sub-pad and the residual test pattern; a bonding pad in the upper dielectric stack and connected to the sub-pad; and a passivation layer covering the upper dielectric stack, wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern, wherein a sidewall of the upper dielectric stack has a stepped region, wherein a top surface of the bonding pad is at a first depth from a top surface of the passivation layer, wherein a bottom surface of the stepped region is at a second depth from the top surface of the passivation layer, and wherein the second depth is about 0.9 times to about 2.0 times the first depth.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor chip with stepped sidewall, semiconductor package including the same, and method of fabricating the same
- Patent number
- US12751277B2
- Application number
- 17882748
- Filed
- Aug 8, 2022
- Granted
- Sep 29, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10D 84/038 Electricity & electronicsH10P 74/273 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/284 Electricity & electronicsH10W 90/297 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.