Samsung patents chip wiring layers using cobalt and ruthenium
Samsung describes a method for building the metal connections inside a semiconductor chip. The design uses specific layers of cobalt and ruthenium to connect upper and lower wiring structures while preventing unwanted electrical contact between different parts.
In the filing’s own words
A semiconductor device may include an upper interlayer insulating film on a lower wiring structure and an upper wiring structure in an upper wiring trench of the upper interlayer insulating film. The lower wiring structure may include a lower filling film and a lower capping film including a capping opening exposing a portion of the lower filling film. The upper wiring structure may contact the lower filling film. The upper wiring structure may include an upper liner between an upper barrier film and an upper filling film. A sidewall portion of the upper liner may include cobalt doped with ruthenium. A bottom portion of the upper liner may not include cobalt doped with ruthenium. A sidewall portion of the upper barrier film may include tantalum nitride doped with ruthenium (Ru). A sidewall portion of the upper barrier film may not be in contact with the lower capping film.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a lower interlayer insulating film including a lower wiring trench; a lower wiring structure including a lower barrier film, a lower liner, a lower filling film, and a lower capping film sequentially disposed on the lower wiring trench, the lower capping film including an upper surface and a bottom surface opposite each other, and the bottom surface of the lower capping film being in contact with an upper surface of the lower filling film; an etch stop film on the lower interlayer insulating film, the etch stop film in contact with an upper surface of the lower interlayer insulating film and the upper surface of the lower capping film; an upper interlayer insulating film on the etch stop film, the upper interlayer insulating film including an upper wiring trench; and an upper wiring structure in the upper wiring trench and in contact with the lower filling film, wherein the upper wiring structure includes an upper barrier film, an upper filling film, and an upper liner between the upper barrier film and the upper filling film, the upper liner includes a sidewall portion and a bottom portion, the sidewall portion of the upper liner extends along a sidewall of the upper wiring trench, the bottom portion of the upper liner extends along a bottom surface of the upper wiring trench, the upper liner includes cobalt (Co), the upper barrier film includes a sidewall portion extending along the sidewall of the upper wiring trench, and the sidewall portion of the upper barrier film includes tantalum nitride doped with ruthenium (Ru), and an upper surface of the lower barrier film is not in contact with the lower capping film.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device including upper and lower wiring structure and method for fabricating thereof
- Patent number
- US12751267B2
- Application number
- 18351779
- Filed
- Jul 13, 2023
- Granted
- Sep 29, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.