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Samsung patents chip method using heavy elements to boost transistor performance

This patent describes a way to build transistors in computer chips by using temporary layers filled with heavy atoms. These layers release specific elements into the chip's structure during manufacturing to improve how electricity flows through the device.

Why it mattersThis technique helps manufacturers create smaller, faster transistors, which is a standard step in making next-generation processors more efficient.

In the filing’s own words

A semiconductor device includes a substrate including an active pattern, a channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, on the active pattern, a source/drain pattern connected to the plurality of semiconductor patterns, and a gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, on the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern, the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first and second portions, the first semiconductor pattern includes a dopant having an atomic weight greater than that of silicon, and a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a substrate including an active region and a dummy region; an active pattern on the active region and a dummy pattern on the dummy region; a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; a dummy stacked pattern on the dummy pattern, the dummy stacked pattern horizontally spaced apart from the channel pattern and the source/drain pattern, and the dummy stacked pattern including a plurality of dummy sacrificial layers and a plurality of dummy layers, wherein the plurality of dummy sacrificial layers and the plurality of dummy layers are alternately stacked; and a gate electrode on the plurality of semiconductor patterns, the gate electrode including an inner electrode interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, wherein each of the plurality of dummy sacrificial layers includes a dopant having an atomic weight greater than an atomic weight of each of silicon-germanium (SiGe) and silicon (Si), and wherein a concentration of the dopant in the plurality of dummy sacrificial layers is in a range from greater than 1.0×10 20 atoms/cm 3 to 1.0×10 21 atoms/cm 3, wherein the plurality of dummy layers include the dopant diffused from the plurality of dummy sacrificial layers, and wherein a concentration of the diffused dopant is 1.0×10 17 atoms/cm 3 to 1.0×10 18 atoms/cm 3.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor device with active layers doped by sacrificial layers and method thereof
Patent number
US12751064B2
Application number
18176170
Filed
Feb 28, 2023
Granted
Sep 29, 2026
Inventors
6
Claims
14

Classified under

H10D 64/017 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6748 Electricity & electronicsH10D 30/6757 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.