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Samsung patents chip design that lowers electrical connections

Samsung has been granted a patent for a specific way to build semiconductor chips. The design uses a two-part connection structure where the top part sits lower than the surrounding gate caps, using a protective layer to separate the parts during manufacturing.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers build smaller and more reliable computer components.

In the filing’s own words

A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

What exactly they claim (claim 1)

1. A method for fabricating a semiconductor device, comprising: forming an active pattern on a substrate, gate structures on the active pattern wherein each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern on the active pattern, and a lower active contact connected to the source/drain pattern; forming a first trench by removing a portion of the lower active contact, wherein an upper surface of the lower active contact exposed by the first trench is lower than an upper surface of the gate capping pattern; forming an etching stop film extending along the upper surface of the lower active contact without contacting the upper surface of the gate capping pattern; and forming an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor device
Patent number
US12751038B2
Application number
18775240
Filed
Jul 17, 2024
Granted
Sep 29, 2026
Inventors
3
Claims
20

Classified under

H10D 30/6211 Electricity & electronicsH10D 62/151 Electricity & electronicsH10W 20/435 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.