Samsung patents stacked memory chip design with direct pad connections
Samsung describes a semiconductor memory device where a memory cell layer is stacked directly under a transistor layer. The two layers are joined by bonding pads that touch each other, creating a direct electrical path between the upper and lower sections.
In the filing’s own words
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a lower substrate; a lower dielectric structure on the lower substrate; a memory cell structure between the lower substrate and the lower dielectric structure; a lower bonding pad in the lower dielectric structure; an upper dielectric structure on the lower dielectric structure; an upper substrate on the upper dielectric structure; a transistor between the upper substrate and the upper dielectric structure; and an upper bonding pad in the upper dielectric structure, wherein: a top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad, and the lower bonding pad and the upper bonding pad overlap the memory cell structure, wherein the memory cell structure includes a cell gate structure, a cell capacitor, and a bit line between the cell gate structure and the cell capacitor, and wherein the upper bonding pad and the lower bonding pad overlap the bit line.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Bonded semiconductor memory device
- Patent number
- US12751020B2
- Application number
- 18370940
- Filed
- Sep 21, 2023
- Granted
- Sep 29, 2026
- Inventors
- 9
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 80/312 Electricity & electronicsH10W 80/327 Electricity & electronicsH10W 90/297 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.