Samsung patents 3D memory stack with mixed-material top layer
Samsung describes a 3D memory chip design where the topmost layer of the vertical stack uses a different material than the layers below it. The filing details how vertical channels penetrate the stack and connect to this top layer, with specific insulating patterns filling the gaps between the channels and the metal.
In the filing’s own words
A three-dimensional semiconductor memory device includes a substrate, a peripheral circuit structure provided on the substrate, and a cell array structure provided on the peripheral circuit structure. The cell array structure includes a stack including alternating interlayer insulating layers and conductive patterns, the conductive patterns including gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns, a second source conductive pattern provided on the stack and in contact with a top surface of the first source conductive pattern, the second source conductive pattern including a material different from a material of the first source conductive pattern, and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern. The vertical channel structures include vertical semiconductor patterns connected to the second source conductive pattern.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor memory device, comprising: a substrate; a peripheral circuit structure provided on the substrate; and a cell array structure provided on the peripheral circuit structure, the cell array structure comprising: a stack comprising alternating interlayer insulating layers and conductive patterns, the conductive patterns comprising gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns; a second source conductive pattern provided as a single layer and on the stack and in direct contact with a top surface of the first source conductive pattern, the second source conductive pattern comprising a material different from a material of the first source conductive pattern; and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern, wherein the vertical channel structures comprise vertical semiconductor patterns connected to the second source conductive pattern and gap-fill insulating patterns covering inner side surfaces of the vertical semiconductor patterns, wherein an upper side surface and the top surface of at least one vertical semiconductor pattern of the vertical semiconductor patterns directly contacts the second source conductive pattern, wherein at least one gap-fill insulating pattern among the gap-fill insulating patterns that covers inner side surfaces of the at least one vertical semiconductor pattern extends into the second source conductive pattern, and wherein a top surface of the at least one gap-fill insulating pattern that extends into the second source conductive pattern directly contacts the at least one vertical semiconductor pattern that directly contacts the second source conductive pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Three-dimensional semiconductor memory device and electronic system including the same
- Patent number
- US12751009B2
- Application number
- 18076090
- Filed
- Dec 6, 2022
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 13
Classified under
H10B 43/27 Electricity & electronicsH10B 43/40 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.