Samsung patents memory chip design with uneven gate layers
Samsung has been granted a patent for a semiconductor device structure used in memory chips. The design features a conductive layer where the section covering a dummy pattern sits higher than the section covering an active cell, creating a stepped surface. This specific arrangement helps manage the physical spacing between different parts of the chip during manufacturing.
In the filing’s own words
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device may include a substrate including first and second cell active patterns and a dummy active pattern, a cell gate dielectric layer on the first and second cell active patterns and the dummy active pattern, a first cell gate conductive layer on the cell gate dielectric layer, and a bit-line structure connected to the first cell active pattern. A distance between the second cell and dummy active patterns is less than that between the first cell and dummy active patterns. The first cell gate conductive layer may include a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern. A top surface of the dummy overlap section may be at a level higher than that of a top surface of the cell overlap section.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including a first cell active pattern, a second cell active pattern, and a dummy active pattern; a cell gate dielectric layer on the first cell active pattern, the second cell active pattern, and the dummy active pattern; a first cell gate conductive layer on the cell gate dielectric layer; and a bit-line structure electrically connected to the first cell active pattern, wherein a distance between the second cell active pattern and the dummy active pattern is less than a distance between the first cell active pattern and the dummy active pattern, wherein the first cell gate conductive layer includes, a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern, and wherein a top surface of the dummy overlap section is at a level higher than a level of a top surface of the cell overlap section.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device comprising cell gate conductive layer with top surface at different levels
- Patent number
- US12751003B2
- Application number
- 18503739
- Filed
- Nov 7, 2023
- Granted
- Sep 29, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10B 12/50 Electricity & electronicsH10B 12/09 Electricity & electronicsH10B 12/315 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.