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Samsung patents memory chip design using layered fence structures

Samsung has been granted a patent for a semiconductor device design that uses a two-layer fence structure to separate components in memory chips. This fence pattern is placed in trenches between bit lines and buried contacts, with each layer made of different materials to manage electrical isolation.

Why it mattersThis is a routine improvement in chip manufacturing that helps maintain the stability of dense memory structures as components get smaller.

In the filing’s own words

A semiconductor device including a word line intersecting and overlapping an active region and extending in a first direction, a word line capping layer on the word line, bit lines interacting and overlapping the active region and extending in a second direction, buried contacts each connected to the active region, direct contacts each connecting the active region to a corresponding one of the bit lines, a fence pattern on top of the word line capping layer, and a landing pad connected to a corresponding one of the buried contacts, wherein the fence pattern is within a fence pattern trench at a corresponding space between a corresponding pair the bit lines and between a corresponding pair the buried contacts, the fence pattern includes a first fence pattern and a second fence pattern on the first fence pattern that include different materials from each other may be provided.

What exactly they claim (claim 1)

1. A semiconductor device, comprising: a substrate including an active region between device separation layers; a word line intersecting and overlapping the active region; a word line capping layer covering a top surface of the word line; a plurality of bit lines interacting and overlapping the active region and extending in a different direction from an extension direction of the word line; a plurality of buried contacts each connected to the active region; a plurality of direct contacts each connecting the active region to a corresponding one of the plurality of bit lines; a fence pattern on top of the word line capping layer; and a landing pad connected to a corresponding one of the plurality of buried contacts, wherein the fence pattern is within a fence pattern trench, the fence pattern trench being at a corresponding space between the plurality of bit lines and between the plurality of buried contacts, a top surface of the word line capping layer is recessed along a bottom surface of the fence pattern trench, the fence pattern includes a first fence pattern and a second fence pattern on the first fence pattern, the first fence pattern includes a first material, and the second fence pattern includes a second material different from the first material.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor device comprising trench gate along with separation layers
Patent number
US12751002B2
Application number
18493267
Filed
Oct 24, 2023
Granted
Sep 29, 2026
Inventors
2
Claims
20

Classified under

H10B 12/482 Electricity & electronicsH10B 12/02 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/485 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.