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Samsung patents chip layer with specific impurity layout

Samsung has been granted a patent for a semiconductor device structure that includes a specific arrangement of impurities within a dielectric layer. The design features two distinct sections where the concentration of these impurities decreases as the layer gets closer to the underlying semiconductor pattern.

Why it mattersThis is a routine improvement in chip manufacturing that likely helps control electrical properties or reduce defects in transistors, but it does not describe a new consumer feature or product.

In the filing’s own words

A semiconductor device includes a semiconductor pattern, a dielectric layer on the semiconductor pattern, and a conductive pattern on the dielectric layer. Each of the semiconductor pattern and the dielectric layer includes impurities. The dielectric layer includes a concentration profile of impurities including a first variation section including a first concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, and a second variation section including a second concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a semiconductor pattern; a dielectric layer on the semiconductor pattern; and a conductive pattern on the dielectric layer, wherein each of the semiconductor pattern and the dielectric layer includes impurities, and wherein the dielectric layer includes a concentration profile of impurities including a first variation section including a first concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, and a second variation section including a second concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, wherein the second variation section is located between the dielectric layer and the semiconductor pattern.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor device
Patent number
US12750999B2
Application number
18619490
Filed
Mar 28, 2024
Granted
Sep 29, 2026
Inventors
6
Claims
20

Classified under

H10B 12/315 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.