Samsung patents clock circuit that adjusts timing using dual voltage checks
This filing describes a phase-locked loop, a circuit that keeps a device's internal clock in sync with a reference signal. It uses a detector that checks the timing gap between two signals and outputs specific voltages and status codes to adjust the clock speed accurately.
In the filing’s own words
A phase-locked loop device and a method for operating the same, including: a voltage-controlled oscillator configured to generate an output clock signal; a divider configured to divide the output clock signal into a first phase division signal; a sampling phase frequency detector configured to: receive a first supply voltage, a second supply voltage different from the first supply voltage, and the first phase division signal, and based on determining that a phase difference between the first phase division signal and a reference clock signal corresponds to a first interval, output a hold voltage and a status signal for the phase difference; a transconductance circuit configured to output a first conversion current based on the hold voltage; a charge pump configured to output a second conversion current based on the status signal; and a loop filter configured to provide a voltage control signal to the voltage-controlled oscillator.
What exactly they claim (claim 1)
1. A phase-locked loop device, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a divider configured to divide the output clock signal into a first phase division signal; a sampling phase frequency detector configured to: receive a first supply voltage, a second supply voltage different from the first supply voltage, and the first phase division signal, and based on determining that a phase difference between the first phase division signal and a reference clock signal corresponds to a first interval, output a hold voltage based on the first supply voltage or the second supply voltage, and output a status signal for the phase difference; a transconductance circuit configured to output a first conversion current based on the hold voltage; a charge pump configured to output a second conversion current based on the status signal; and a loop filter configured to provide a voltage control signal corresponding to the first conversion current and the second conversion current to the voltage-controlled oscillator.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Phase-locked loop device, and operating method of the device
- Patent number
- US12750061B2
- Application number
- 18904828
- Filed
- Oct 2, 2024
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H03L 7/0895 Electricity & electronicsH03L 7/099 Electricity & electronicsH03L 7/1077 Electricity & electronicsH03L 7/18 Electricity & electronicsH03K 19/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.