Samsung patents memory chip that self-adjusts timing accuracy
This filing describes a memory chip design that uses two separate internal loops to fix timing errors. One loop adjusts the phase of the signal to align it correctly, while the other corrects the duty cycle, which is the balance between the signal's on and off times.
In the filing’s own words
A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).
What exactly they claim (claim 1)
1. A memory device, comprising: a memory chip configured to perform a phase calibration operation and a duty cycle correction operation, during a training section, said memory chip comprising: a first loop circuit, including: a phase detector configured to generate a first comparison signal by detecting a phase difference between a first signal and a second signal, which are received from external the memory chip; a first counter configured to generate a delay signal in response to the first comparison signal; and a delay cell configured to perform the phase calibration operation on the first signal, in response to the delay signal; and a second loop circuit, including: a phase generator configured to generate a second reverse signal in response to the second signal; the phase detector configured to generate a second comparison signal by comparing a duty cycle of a first reverse signal received from external the memory chip with a duty cycle of the second reverse signal; a second counter configured to generate a control signal in response to the second comparison signal; and a duty correction circuit (DCC) configured to perform the duty cycle correction operation on the second signal according to the control signal.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device and storage device including the same
- Patent number
- US12750060B2
- Application number
- 18897676
- Filed
- Sep 26, 2024
- Granted
- Sep 29, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H03L 7/0818 Electricity & electronicsG11C 7/1069 Physics & computingH03L 7/085 Electricity & electronicsH03L 7/195 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.