Microsoft patents chip clocking method using a voltage sensor
Microsoft has been granted a patent for a specific way to manage the internal clock of a computer chip. The design uses a sensor to monitor the power supply and adjust the clock's operation based on that voltage reading.
In the filing’s own words
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.
What exactly they claim (claim 1)
1. A device, comprising: a phase locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) and a phase detector; and a voltage supply and transconductance (Gm) cell that, in operation, drains a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm cell, wherein the Gm cell, in operation, generates an open_loop signal based on the Iout drained from the VCO, and the open_loop signal is input into the phase detector of the PLL to switch the operation of the PLL between an open loop state and a closed loop state.
Facts
- Company
- Microsoft (Microsoft Technology Licensing, LLC)
- Official title
- Clocking system for a system on chip using PLL
- Patent number
- US12750059B2
- Application number
- 18756905
- Filed
- Jun 27, 2024
- Granted
- Sep 29, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H03L 7/0816 Electricity & electronicsH03L 7/0805 Electricity & electronicsH03L 7/083 Electricity & electronicsMore from Microsoft in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.