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Google patents faster flip-flop design for computer chips

This patent describes a specific circuit design for a flip-flop, a tiny component that stores data in computer chips. It combines two different internal paths, one for speed and one for stability, to allow the chip to run at higher speeds without extra parts.

Why it mattersIt offers a more efficient way to build basic computer components, which could lead to slightly faster or more power-efficient processors.

In the filing’s own words

Techniques and apparatuses are described that implement a flip-flop with a high-speed architecture. In example aspects, the high-speed architecture of the flip-flop is a two-path architecture, which represents a hybrid combination of multiple topologies controlled by different clock signals. At a first path of the flip-flop, the high-speed architecture has a pulsed-latch topology, which enables the flip-flop to have a smaller insertion delay relative to other flip-flops with a single-path architecture based on the master-slave topology. At a second path of the flip-flop, the high-speed architecture has a master-slave topology to satisfy the hold time requirement of the flip-flop without relying on additional buffers. The high-speed architecture can be used to implement a scan-type flip-flop, including settable and/or resettable versions of the scan-type flip-flop. With the high-speed architecture, the flip-flop can operate at higher clock frequencies compared to other flip-flops with single-path architectures.

What exactly they claim (claim 1)

1. An apparatus comprising: a flip-flop having an architecture comprising: a first path having a pulsed-latch topology between a first input of the flip-flop and an output of the flip-flop, the pulsed-latch topology controlled by a first clock signal having a first duty cycle, the pulsed-latch topology comprising a single latch between the first input and the output, the single latch comprising a first pass-gate circuit; a second path having a master-slave topology between a second input of the flip-flop and the output of the flip-flop, the master-slave topology controlled by a second clock signal having a second duty cycle that is greater than the first duty cycle, the master-slave topology comprising two latches, the two latches comprising pass-gate circuits that are distinct from the first pass-gate circuit of the pulsed-latch topology; and a keeper circuit that is coupled between a shared node of the flip-flop and the output, the keeper circuit existing within the first and second paths, the keeper circuit representing a portion of the pulsed-latch topology and representing a portion of the master-slave topology.

Facts

Company
Google (Google LLC)
Official title
Flip-flop with a high-speed architecture
Patent number
US12750043B2
Application number
18899902
Filed
Sep 27, 2024
Granted
Sep 29, 2026
Inventors
4
Claims
20

Classified under

H03K 3/356 Electricity & electronicsH03K 3/0372 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.