Samsung patents memory chip that checks itself at different speeds
This patent describes a method for flash memory chips to write data more efficiently. It allows different sections of the chip to be checked at different frequencies during the writing process, depending on how well the data was stored in previous steps.
In the filing’s own words
A memory device includes control logic configured to control memory cell planes based on a determination result, wherein the control logic is further configured to, in response to the determination result for a first program loop in which a first memory cell plane is determined to be program-passed and a second memory cell plane is determined to be program-failed through a first verify voltage for a first program state, control the memory cell planes so that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop performed sequentially after the first program loop.
What exactly they claim (claim 1)
1. A memory device comprising: a voltage generator configured to generate voltages for a plurality of program loops for memory cells, wherein each of the plurality of program loops comprises a program operation and at least one verify operation, wherein the at least one verify operation uses one of a plurality of verify voltages for verifying a plurality of program states; a plurality of memory cell planes each comprising a plurality of memory cells, the plurality of memory cell planes each configured to perform the plurality of program loops in response to the plurality of verify voltages and output a determination result corresponding to the at least one verify operation for each of the plurality of program loops; and control logic configured to control the plurality of memory cell planes based on the determination result, wherein the control logic is further configured to, based on the determination result regarding a first program loop of the plurality of program loops in which (i) a first memory cell plane of the plurality of memory cell planes is determined to be program-passed and (ii) a second memory cell plane of the plurality of memory cell planes is determined to be program-failed through a first verify voltage of the plurality of verify voltages for a first program state of the plurality of program states, control the memory cell planes such that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop of the plurality of program loops performed sequentially after the first program loop.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Memory device, memory system including the same, and operating method of the memory device
- Patent number
- US12749535B2
- Application number
- 18952707
- Filed
- Nov 19, 2024
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G11C 16/10 Physics & computingG11C 16/30 Physics & computingG11C 16/3459 Physics & computingG11C 16/0483 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.