Samsung patents memory chip design using NOR logic for faster data access
Samsung has been granted a patent for a specific circuit design inside memory chips, such as those found in phones and computers. The invention describes a row decoder that uses a NOR logic circuit to split address signals into main and sub-components, allowing the chip to activate the correct data row more efficiently.
In the filing’s own words
A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.
What exactly they claim (claim 1)
1. A memory device, comprising: a plurality of memory blocks comprising a plurality of word lines; and a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks, wherein the row decoder comprises: a main word line driver circuit commonly electrically connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals; and a sub-word line driver circuit electrically connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are electrically connected, wherein the main word line driver circuit comprises: a first main word line driving signal generation circuit configured to generate the first main word line driving signals based on a subset of signals of a most significant bit group from among the row address signals; a second main word line driving signal generation circuit configured to generate the second main word line driving signals based on remaining signals, not included in the subset of signals, of the most significant bit group from among the row address signals; and a first sub-word line driving signal generation circuit and a second sub-word line driving signal generation circuit configured to generate first sub-word line driving signals and second sub-word line driving signals, respectively, based on remaining signals of a least significant bit group from among the row address signals, the first sub-word line driving signals and the second sub-word line driving signals having complementary logic levels relative to each other, and wherein the sub-word line driving signals comprise the first sub-word line driving signals and the second sub-word line driving signals.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory devices including row decoder circuits having sub-word line driver circuit with nor logic circuit
- Patent number
- US12749524B2
- Application number
- 18781150
- Filed
- Jul 23, 2024
- Granted
- Sep 29, 2026
- Inventors
- 3
- Claims
- 19
Classified under
G11C 11/4087 Physics & computingG11C 11/4085 Physics & computingH03K 19/20 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.