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Google patents display tech that syncs pixel updates across the screen

Google describes a display backplane design that uses specific electrical circuits to slow down signals traveling to different parts of the screen. By adding calculated delays to the horizontal and vertical lines, the system ensures that all pixels receive their update commands at the exact same time, regardless of their physical location.

Why it mattersThis improves the consistency of image quality in large displays by preventing timing mismatches between pixels.

In the filing’s own words

A backplane including bit lines and word lines to update a radiative state of a pixel is disclosed. The back plane includes a first delay line that replicates delays caused by a bit line and a second delay line that replicates delays caused by a word line. The replicated delays cause word line signals traveling along a first path to arrive at a pixel at approximately the same time as bit line signals traveling along a second path. The delays are added incrementally row-by-row and column-by-column so that each pixel can receive synchronized signals regardless of its position in the array of pixels.

What exactly they claim (claim 1)

1. A backplane for a display, the backplane comprising: pixels in a two-dimensional array; word lines coupled to rows of pixels in the two-dimensional array; a first delay line including a first plurality of delay elements connected in series, the word lines being connected to respective outputs of corresponding delay elements of the first delay line, wherein each delay element of the first plurality of delay elements includes a first resistor-capacitor circuit; bit lines coupled to columns of pixels; and a second delay line including a second plurality of delay elements connected in series, each bit line connected to an output of a corresponding delay element of the second delay line, wherein each delay element of the second plurality of delay elements includes a second resistor-capacitor circuit.

Facts

Company
Google (Google LLC)
Official title
Signal synchronization for a display
Patent number
US12749433B2
Application number
18920286
Filed
Oct 18, 2024
Granted
Sep 29, 2026
Inventors
4
Claims
19

Classified under

G09G 3/32 Physics & computingG09G 2300/0857 Physics & computingG09G 2310/08 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.