Samsung patents chip design that splits math tasks to save power
This patent describes a hardware setup that performs basic math operations for neural networks using a grid of memory cells. It uses a mathematical method to split the grid into smaller parts, which allows the system to process data more efficiently than using the full grid every time.
In the filing’s own words
A compressed-truncated singular value decomposition (C-TSVD) based crossbar array apparatus is provided. The C-TSVD based crossbar array apparatus may include an original crossbar array in an m×n matrix having row input lines and column output lines and including cells of a resistance memory device, or two partial crossbar arrays obtained by decomposing the original crossbar array based on C-TSVD, an analog to digital converter (ADC) that converts output values of column output lines of sub-arrays obtained through array partitioning, an adder that sums up results of the ADC to correspond to the column output lines, and a controller that controls application of the original crossbar array or the two partial crossbar arrays. Input values are input to the row input lines, a weight is multiplied by the input values and accumulated results are output as output values of the column output lines.
What exactly they claim (claim 1)
1. An analog multiply-accumulate (MAC) operation method comprising: calculating an original crossbar array in an m×n matrix having n row input lines and m column output lines, the matrix including cells of a resistance memory device, where n and m are natural numbers; selectively performing compressed-truncated singular value decomposition (C-TSVD) decomposing the original crossbar array into two partial crossbar arrays; partitioning the original crossbar array into sub-arrays, or partitioning the two partial crossbar arrays into sub-arrays, in accordance with a result of selectively performing the C-TSVD; inputting input values to row input lines of the sub-arrays; multiplying a weight by the input values and accumulating multiplication results in the sub-arrays and outputting output values to the column output lines of the sub-arrays; analog to digital (AD) converting the output values of the column output lines by using an analog to digital converter (ADC); and summing up the ADC results to correspond to the column output lines by using an adder, wherein a crossbar array apparatus corresponding to one layer of a neural network is used in neuromorphic computing, wherein the crossbar array apparatus comprises the original crossbar array or the two partial crossbar arrays, the ADC, the adder, and a controller, and wherein, in the selectively performing of the C-TSVD, application of the original crossbar array or the two partial crossbar arrays is controlled by the controller.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Crossbar array apparatuses based on compressed-truncated singular value decomposition (C-TSVD) and analog multiply-accumulate (MAC) operation methods using the same
- Patent number
- US12748962B2
- Application number
- 19030176
- Filed
- Jan 17, 2025
- Granted
- Sep 29, 2026
- Inventors
- 2
- Claims
- 10
Classified under
G06N 3/065 Physics & computingG06F 7/5443 Physics & computingG06F 17/16 Physics & computingG06N 3/049 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.