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Microsoft patents circuit that adjusts timing precision to sync signals

Patent drawing
Patent drawing from the official filing.

Microsoft has been granted a patent for a time-to-digital converter circuit that measures tiny differences in signal timing. The design switches between a coarse mode for larger time gaps and a fine mode for smaller gaps to maintain accuracy. This helps a digital oscillator correct its frequency to stay synchronized with a reference signal.

Why it mattersThis improves the internal timing precision of electronic components, which is essential for stable communication in devices like phones and computers.

In the filing’s own words

A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the digitally controlled oscillator (DCO) to correct for the phase/frequency difference to synchronize the generated signal with the reference signal. In an aspect, an adaptive TDC circuit generates a first digital indication in a coarse mode when the offset time is above a threshold and generates a second digital indication in a fine mode when the offset time is below the threshold. The first digital indication and the second digital indication each comprise a same number of bits, and the first digital indication is normalized to the second digital indication for the digital output of the adaptive TDC circuit. A fractional bit may be employed to compensate for a quantization error.

What exactly they claim (claim 1)

1. An adaptive time-to-digital converter (TDC) circuit, comprising: a first series of serially coupled first delay circuits, the first series comprising a first series input and a first series output, wherein each of the first delay circuits is configured to provide a first signal delay from a first delay input to a first delay output; a second series of serially coupled second delay circuits, the second series comprising a second series input and a second series output, wherein each of the second delay circuits is configured to provide a second signal delay from a second delay input to a second delay output; a plurality of first storage circuits, each first storage circuit comprising: a first clock input coupled to the second series input; a first data input coupled to the first delay output of a corresponding one of the first delay circuits in the first series; and a first data output coupled to a first decoder; and a plurality of second storage circuits, each second storage circuit comprising: a second clock input coupled to the second delay output of a corresponding one of the second delay circuits in the second series; a second data input coupled to the first delay output of a corresponding one of the first delay circuits in the first series; and a second data output coupled to a second decoder; wherein: the first decoder is configured to generate a first indication of a first time period from a first start signal on the first series input to a first stop signal on the second series input; and the second decoder is configured to generate a second indication of a second time period from a second start signal on the first series input to a second stop signal on the second series input.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods
Patent number
US12748385B2
Application number
19018950
Filed
Jan 13, 2025
Granted
Sep 29, 2026
Inventors
2
Claims
20

Classified under

G04F 10/005 Physics & computingH03L 7/103 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.