Samsung patents chip stack design that layers memory directly on logic
This patent describes a semiconductor package that stacks a logic chip and a memory chip vertically using multiple layers of wiring. The design uses specific redistribution layers to connect the memory chip directly to the logic chip, allowing them to share data without moving through the main circuit board.
In the filing’s own words
A semiconductor package includes a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface, a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer, a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires, and a semiconductor substrate disposed on an upper surface of the third redistribution wire layer, the semiconductor substrate including at least one memory semiconductor chip electrically connected to the fourth redistribution wires.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface; a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer; a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires; and a semiconductor substrate disposed on an upper surface of the third redistribution wiring layer, the semiconductor substrate including at least one memory semiconductor chip directly contacting the fourth redistribution wires.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package and method of manufacturing the semiconductor package
- Patent number
- US12745685B2
- Application number
- 18223757
- Filed
- Jul 19, 2023
- Granted
- Sep 22, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 90/701 Electricity & electronicsH10W 70/093 Electricity & electronicsH10W 70/095 Electricity & electronicsH10W 70/635 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.