Samsung patents chip stack design with smaller glue layers

1. A semiconductor package comprising: a base chip including lower pads on a lower surface, upper pads on an upper surface, and through-electrodes electrically connecting the lower pads and the upper pads to each other; a first semiconductor chip on the base chip, the first semiconductor chip including first front pads on a first front surface, first back pads on a first back surface, and first through-vias electrically connecting the first front pads and the first back pads to each other; first bump structures on the first front surface of the first semiconductor chip, the first bump structures electrically connecting the first front pads and the upper pads to each other; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips each including second front pads on second front surfaces, second back pads on second back surfaces, and second through-vias electrically connecting the second front pads and the second back pads to each other; second bump structures on a second front surface of each of the plurality of second semiconductor chips, the second bump structures electrically connecting at least some pads facing each other among the first back pads, the second front pads, and the second back pads; adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, the adhesive layers surrounding the second bump structures; and an encapsulant surrounding the first bump structures between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips, wherein the adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip, and wherein a first distance between the base chip and the first semiconductor chip is greater than a second distance between the first semiconductor chip and a lowermost second semiconductor chip, among the plurality of second semiconductor chips.