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Samsung patents chip stacking design with shaped connection pads

Samsung describes a method for stacking two computer chips vertically using a technique called hybrid bonding. The design uses square-shaped connection points in the center of the chips and elongated, rectangular points near the corners. These corner pads are oriented sideways relative to the chip's center to improve the physical connection between the layers.

Why it mattersThis is a detailed engineering improvement for making stacked chips more stable, which is a standard part of developing faster and smaller processors.

In the filing’s own words

A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a lower chip including a lower bonding insulation layer, a first lower bonding pad, and a second lower bonding pad; and an upper chip disposed on the lower chip, the upper chip including an upper bonding insulation layer, a first upper bonding pad, and a second upper bonding pad respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad, wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length, and the first lower bonding pad and the first upper bonding pad are disposed one-dimensionally or planarily in a first center region which is near a center point of the lower chip and the upper chip, each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length, and the second lower bonding pad and the second upper bonding pad are disposed one-dimensionally or planarily in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor package
Patent number
US12745678B2
Application number
18387656
Filed
Nov 7, 2023
Granted
Sep 22, 2026
Inventors
3
Claims
20

Classified under

H10W 90/00 Electricity & electronicsH10W 72/90 Electricity & electronicsH10W 72/926 Electricity & electronicsH10W 72/932 Electricity & electronicsH10W 72/936 Electricity & electronicsH10W 72/944 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.