Samsung patents chip layout that isolates connection points
This patent describes a specific layout for the base board used to hold computer chips. It places metal connection points between two chips and uses a gap in the metal wiring to stop electrical signals from leaking between them.
In the filing’s own words
A substrate for a semiconductor package includes a semiconductor chip mounting region; a bonding terminal region including at least one bonding terminal; at least one plating line extending across the semiconductor chip mounting region; a plating line prohibition region at an opposite side of the bonding terminal region from the semiconductor chip mounting region; and a plating line removal region that is between the bonding terminal region and the semiconductor chip mounting region and is free of a portion of the plating line so that each of the at least one bonding terminal is electrically isolated.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate including a plurality of bonding terminals and a plating line on one surface of the substrate; a first semiconductor chip that is mounted on the one surface of the substrate and includes a plurality of bonding pads formed near at least one edge on a top surface of the first semiconductor chip; and a second semiconductor chip that is mounted on the one surface of the substrate at a distance from the first semiconductor chip, and includes a plurality of bonding pads formed near at least one edge on a top surface of the second semiconductor chip, wherein, the plurality of bonding terminals are between the first semiconductor chip and the second semiconductor chip and are connected to the plurality of bonding pads of the first semiconductor chip and the plurality of bonding pads of the second semiconductor chip by wires, the plating line is between the plurality of bonding terminals and the first semiconductor chip and is connected to each of the plurality of bonding terminals, and a plating line removal region is between the first semiconductor chip and the plurality of bonding terminals and is free of a portion of the plating line so that each of the plurality of bonding terminals is electrically isolated.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Substrate for semiconductor package and semiconductor package including the same
- Patent number
- US12745676B2
- Application number
- 18331977
- Filed
- Jun 9, 2023
- Granted
- Sep 22, 2026
- Inventors
- 2
- Claims
- 15
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 90/752 Electricity & electronicsH10W 90/753 Electricity & electronicsH10W 90/754 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.