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Samsung patents chip packaging method using spacers for better alignment

Samsung describes a way to build semiconductor packages by attaching small passive components to a base using solder and a central insulating spacer. This spacer helps hold the component in place while a separate chip is attached nearby, keeping the parts spaced apart.

Why it mattersThis is a routine manufacturing improvement that helps ensure components are placed correctly during chip production.

In the filing’s own words

A method of manufacturing a semiconductor package includes; positioning a passive element on an upper insulating layer of a package substrate, wherein the upper insulating layer of the package substrate exposes upper surfaces of first substrate pads and second substrate pads, the passive element includes; electrodes on respective corners of a lower surface of the passive element, solder members respectively on the electrodes, and an insulating spacer on a central portion of the lower surface of the passive element between the solder members, and the solder members are respectively disposed on the second substrate pads. The method further includes; bonding the passive element on the package substrate through the solder members and the second substrate pads, and bonding a semiconductor device to the first substrate pads on the package substrate through conductive bumps on a lower surface of the semiconductor device, wherein the semiconductor device is laterally spaced apart from the passive element on the package substrate.

What exactly they claim (claim 1)

1. A method of manufacturing a semiconductor package, the method comprising: positioning at least one semiconductor element on an upper insulating layer of a package substrate, wherein the upper insulating layer of the package substrate exposes upper surfaces of first substrate pads and second substrate pads, each semiconductor element among the at least one semiconductor element includes electrodes on a lower surface of the at least one semiconductor element and respectively disposed in a peripheral region of the semiconductor element, solder members respectively on the electrodes, and an insulating spacer attached on the lower surface of the semiconductor element and disposed in a central portion of the semiconductor element between the solder members, wherein the insulating spacer extends outwardly from a center of the lower surface of the semiconductor element, and the solder members are respectively disposed on the second substrate pads; bonding the at least one semiconductor element on the package substrate using the solder members, thereby causing the insulating spacer to contact the package substrate, wherein the insulating spacer is spaced apart from the package substrate before bonding the at least one semiconductor element on the package substrate; and bonding a semiconductor device on the package substrate, wherein the semiconductor device is laterally spaced apart from the semiconductor element on the package substrate.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor package and method of manufacturing
Patent number
US12745652B2
Application number
18118303
Filed
Mar 7, 2023
Granted
Sep 22, 2026
Inventors
2
Claims
15

Classified under

H10W 70/093 Electricity & electronicsH10W 70/05 Electricity & electronicsH10W 70/095 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 70/69 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.