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Samsung patents chip design using germanium to boost transistor speed

Samsung has secured a patent for a semiconductor design that adds a specific layer of germanium to the transistors inside a chip. The filing describes a structure where the amount of germanium changes as you move away from the base, which helps electrons move more easily through the device.

Why it mattersThis is a standard improvement in chip manufacturing that aims to make transistors work more efficiently, potentially leading to faster or more power-efficient processors in future devices.

In the filing’s own words

A semiconductor device includes a substrate including a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region, a first active pattern on the PMOSFET region, a second active pattern on the NMOSFET region, a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern, a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern, and a gate electrode on the first channel pattern and the second channel pattern.

What exactly they claim (claim 1)

1. A semiconductor device, comprising: a substrate comprising a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region; a first active pattern on the PMOSFET region; a second active pattern on the NMOSFET region; a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern; a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern; and a gate electrode on the first channel pattern and the second channel pattern, wherein the first source/drain pattern comprises a first buffer layer and a first main layer on the first buffer layer, wherein the second source/drain pattern comprises a second buffer layer and a second main layer on the second buffer layer, wherein each of the first buffer layer and the second buffer layer comprises silicon-germanium (SiGe), wherein a germanium concentration in each of the first buffer layer and the second buffer layer is in a range from 2 at % to 30 at %, wherein a germanium concentration of the first source/drain pattern increases in a first direction that is away from the substrate, and wherein a germanium concentration in the second source/drain pattern decreases in the first direction.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor device including source/drain pattern with main layer and buffer layer having germanium and method of fabricating the same
Patent number
US12745452B2
Application number
18227064
Filed
Jul 27, 2023
Granted
Sep 22, 2026
Inventors
7
Claims
14

Classified under

H10D 84/85 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 62/405 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.