Samsung patents semiconductor design with stacked channels and dummy gates
This patent describes a specific layout for a semiconductor device, which is the basic building block of computer chips. It details how to arrange the gate, channel, and isolation layers, including a 'dummy' gate and a separation pattern, to manage the physical structure of the transistor.
In the filing’s own words
Disclosed is a semiconductor device including: a substrate including a first active pattern separated into a pair of first active patterns by a trench; a device isolation layer filling the trench; first source/drain patterns on the first active pattern; a first channel pattern connected to the first source/drain patterns and including semiconductor patterns; a first dummy gate electrode that extends while being adjacent to a first sidewall of the trench; a gate electrode that is spaced apart in the first direction from the first dummy gate electrode and extends while running across the first channel pattern, a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending between the gate electrode and the first dummy gate electrode. A top surface of the separation pattern is at a same level as that of the gate capping pattern.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate comprising a first active pattern extending in a first direction, the first active pattern being separated into a pair of first active patterns by a trench extending in a second direction intersecting the first direction; a device isolation layer that fills a lower portion of the trench; a plurality of first source/drain patterns on the first active pattern; a first channel pattern connected to the plurality of first source/drain patterns, the first channel pattern comprising a plurality of semiconductor patterns that are stacked and spaced apart from each other; a first dummy gate electrode extending in the second direction, and being adjacent to a first sidewall of the trench; a gate electrode spaced apart in the first direction from the first dummy gate electrode, the gate electrode extending in the second direction across the first channel pattern; a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending in the second direction between the gate electrode and the first dummy gate electrode, wherein, in the first direction, the separation pattern is between adjacent ones of the plurality of first source/drain patterns, wherein a top surface of the separation pattern is at a same level as a top surface of the gate capping pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12745451B2
- Application number
- 17868401
- Filed
- Jul 19, 2022
- Granted
- Sep 22, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/031 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.