Samsung patents chip design mixing wide and narrow silicon channels
This patent describes a semiconductor structure that combines two types of vertical silicon channels on a single chip. The design uses wider channels alongside narrower ones, with specific spacing and material volumes between them to control how electricity flows through the device.
In the filing’s own words
A semiconductor device may include a plurality of first channel structures on a substrate, a plurality of second channel structures on the substrate, a first impurity region structure between the first channel structures, a second impurity region structure between second channel structures, a third impurity region structure between the first and second channel structures, and a plurality of gate structures disposed between the first to third impurity region structures, respectively. Each of the first channel structure may have a first width, and each of the second channel structure may have a second width less than the first width. The first impurity region structure may have a first volume, and the second impurity region structure may have a second volume smaller than the first volume. The third impurity region structure may have a third volume smaller than the first volume and greater than the second volume.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a plurality of first channel structures on a substrate, the first channel structures spaced apart from each other in a first direction parallel to a surface of the substrate, each of the first channel structure having a first width in a second direction parallel to the surface of the substrate and perpendicular to the first direction, and including silicon patterns spaced apart from each other in a vertical direction; a plurality of second channel structures on the substrate, the second channel structures spaced apart from each other in the first direction, each of the second channel structure having a second width in the second direction less than the first width, and including silicon patterns spaced apart from each other in the vertical direction; a first impurity region structure between the first channel structures, the first impurity region structure connecting sidewalls of adjacent first channel structures, and having a first volume; a second impurity region structure between second channel structures, the second impurity region structure connecting sidewalls of adjacent second channel structures, and having a second volume smaller than the first volume; a third impurity region structure between the first and second channel structures, the third impurity region structure connecting sidewalls of adjacent first and second channel structures, and having a third volume smaller than the first volume and greater than the second volume; and a plurality of gate structures disposed between the first to third impurity region structures, respectively, each of the gate structure covering one of the first and second channel structures, and extending in the second direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device with channel structures and impurity region structures
- Patent number
- US12745450B2
- Application number
- 18318587
- Filed
- May 16, 2023
- Granted
- Sep 22, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/83 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/235 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.