Samsung patents chip design with taller insulating walls between gates
This patent describes a semiconductor structure where the insulating material separating two gate electrodes is built higher than the gates themselves. The design ensures this insulating layer reaches the same height as the electrical contacts, creating a clear physical barrier between adjacent components.
In the filing’s own words
A semiconductor device includes a substrate including an active pattern, first and second source/drain patterns overlapping with the active pattern, a separation insulating layer between the first and second source/drain patterns, and first and second gate electrodes spaced apart from each other with the separation insulating layer interposed therebetween. A level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; an active pattern on the substrate; a first source/drain pattern and a second source/drain pattern which overlap with the active pattern; a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, a separation insulating layer between the first source/drain pattern and the second source/drain pattern and between the first active contact and the second active contact, the separation insulating layer physically and electrically separating the first active contact from the second active contact; a first gate electrode and a second gate electrode which are spaced apart from each other with the separation insulating layer interposed therebetween, wherein a level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode, and wherein the level of the top surface of the separation insulating layer is substantially the same as a level of a top surface of the first active contact and a level of a top surface of the second active contact.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12745421B2
- Application number
- 18500499
- Filed
- Nov 2, 2023
- Granted
- Sep 22, 2026
- Inventors
- 6
- Claims
- 18
Classified under
H10D 30/6729 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.