Samsung patents 3D chip stacking method with internal separation layers

1. A method for manufacturing a semiconductor device, the method comprising: preparing a first semiconductor structure by forming circuit devices on a first substrate; forming a second substrate, constituting a second semiconductor structure, on the first semiconductor structure; forming a first stack region of a stack structure by alternately stacking first interlayer insulating layers and first sacrificial layers, extending in a first direction, on an upper surface of the second substrate; forming a second stack region of the stack structure by alternately stacking second interlayer insulating layers and second sacrificial layers, extending in the first direction, on the first stack region; forming first openings spaced apart from each other in the first direction by partially removing the second stack region; forming a first filling insulating layer completely filling the first openings; forming a second opening by partially removing the second stack region between the first openings in the first direction; removing the second sacrificial layers exposed through the second opening; forming a lower separation region including the first filling insulating layer and a second filling insulating layer, by forming the second filling insulating layer filling the second opening and regions between vertically-adjacent second interlayer insulating layers in which the second sacrificial layers have been removed; forming a third stack region of the stack structure by alternately stacking third interlayer insulating layers and third sacrificial layers, extending in the first direction, on the first and second filling insulating layers; forming channel structures passing through the stack structure; forming third openings passing through the stack structure, extending in the first direction, and exposing a portion of the first and second filling insulating layers of the lower separation region; removing the first to third sacrificial layers exposed through the third openings; and forming first to third gate electrodes by respectively filling a conductive material in regions in which the first to third sacrificial layers have been removed.