Samsung patents chip design with layered contacts to improve memory connections
Samsung describes a semiconductor structure that uses a trench to connect a bit line to the active area of a chip. The design includes three layers of insulating material around the contact point, with the outer two layers broken into separate sections to manage electrical isolation.
In the filing’s own words
A semiconductor device includes a substrate that includes an element separation film, an active region defined by the element separation film and arranged in a first direction, and a trench positioned across the active region and the element separation film, a bit line contact that is positioned within the trench and is connected to the active region, a bit line structure that is connected to the substrate through the bit line contact and that extends in a second direction different from the first direction across the active region, and a first contact spacer, a second contact spacer, and a third contact spacer within the trench and around the bit line contact, the first contact spacer being continuous within the trench, and each of the second contact spacer and the third contact spacer being separated into at least two discrete parts within the trench.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate that includes an element separation film, an active region defined by the element separation film and arranged in a first direction, and a trench positioned across the active region and the element separation film; a bit line contact that is positioned within the trench and is connected to the active region; a bit line structure that is connected to the substrate through the bit line contact and that extends in a second direction different from the first direction across the active region; and a first contact spacer, a second contact spacer, and a third contact spacer within the trench and around the bit line contact, the first contact spacer being continuous around a sidewall of the bit line contact within the trench and surrounding the entire perimeter of the bit line contact, and each of the second contact spacer and the third contact spacer being separated into at least two discrete parts within the trench, wherein the first contact spacer is spatially separated from the bit line contact.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor apparatus having multi-layered bit line contact and manufacturing method of the same
- Patent number
- US12745386B2
- Application number
- 18216745
- Filed
- Jun 30, 2023
- Granted
- Sep 22, 2026
- Inventors
- 7
- Claims
- 11
Classified under
H10B 12/485 Electricity & electronicsH10B 12/053 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/482 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.