/Patent Tracker
SamsungGranted patentChips & hardwareInterest 3/10

Samsung patents circuit that adjusts clock speed for stable signals

This patent describes a phase-locked loop circuit that keeps electronic clocks running at a steady rate. It uses a switch to change the circuit's resistance once the clock signal is stable, helping to filter out noise and maintain accuracy.

Why it mattersThis is a routine improvement to internal chip components that helps ensure digital devices process data reliably without timing errors.

In the filing’s own words

There is provided a phase locked loop circuit including a phase-frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on first phase difference, and generate a first and a second control signals based on the phase gain, a lock detection circuit configured to generate a lock detection signal based on the first phase difference, a charge pump circuit configured to generate a loop filter input signal based on the first and second control signals, a loop filter configured to adjust impedance based on the activated lock detection signal and generate a loop filter output signal based on the adjusted impedance, an oscillator configured to generate a clock signal based on the loop filter output signal, and a divider configured to generate the feedback clock signal by dividing the clock signal.

What exactly they claim (claim 1)

1. A phase locked loop circuit comprising: a phase-frequency detection circuit configured to: receive a reference clock signal and a feedback clock signal, adjust a phase gain from a first value to a second value in response to a phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and generate a first control signal and a second control signal based on the phase gain; a lock detection circuit configured to generate a lock detection signal that is activated in response to the phase gain having the second value; a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal; a loop filter comprising at least one resistor, at least one capacitor, and a first switch connected in series with the at least one resistor, the loop filter configured to: adjust impedance by switching the first switch based on the activated lock detection signal, and generate a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance; an oscillator configured to generate a clock signal based on the loop filter output signal; and a divider configured to generate the feedback clock signal by dividing the clock signal.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Phase locked loop circuit and method of operation thereof
Patent number
US12744539B2
Application number
18804954
Filed
Aug 14, 2024
Granted
Sep 22, 2026
Inventors
5
Claims
20

Classified under

H03L 7/1077 Electricity & electronicsH03L 7/0891 Electricity & electronicsH03L 7/095 Electricity & electronicsH03L 7/1075 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

More from Samsung in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.