Samsung patents memory chip that performs math inside the storage cells
This filing describes a memory device where the storage cells are designed to handle basic calculations directly, rather than just holding data. Each cell uses transistors with specific electrical strengths based on powers of two, allowing the hardware to process information without moving it to a separate processor.
In the filing’s own words
A memory device includes an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including bit cells. Each of the plurality of bit cells includes a first transistor having one end connected to a corresponding write bit line, the other end connected to a storage node, and a gate terminal connected to the write word line, and at least one second transistor having one end connected to the read bit line, the other end connected to the read word line, and a gate terminal connected to the storage node. A current value of turn-on current of the at least one second transistor included in each of the bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2 that is different for each of the bit cells.
What exactly they claim (claim 1)
1. A memory device comprising: an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including a plurality of bit cells; wherein each of the plurality of bit cells comprises: a first transistor having a first end connected to a corresponding write bit line among the plurality of write bit lines, a second end connected to a storage node, and a gate terminal connected to the write word line; and at least one second transistor having a first end connected to the read bit line, a second end connected to the read word line, and a gate terminal connected to the storage node, wherein a current value of a turn-on current of the at least one second transistor included in each of the plurality of bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2, and wherein the power of 2 is different for each of the plurality of bit cells.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device including in-memory operation circuit and operating method thereof
- Patent number
- US12744071B2
- Application number
- 18985730
- Filed
- Dec 18, 2024
- Granted
- Sep 22, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G11C 11/405 Physics & computingG11C 7/16 Physics & computingG11C 11/4085 Physics & computingG11C 11/4091 Physics & computingG11C 11/4096 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.