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SamsungGranted patentChips & hardwareInterest 4/10

Samsung patents AI method to speed up chip layout checks

This patent describes a method for checking the design of computer chips before they are built. It uses a machine learning model trained on data from a standard simulator to quickly verify that the chip's layout works correctly.

Why it mattersIt could help chip designers find errors in their designs faster, saving time during the manufacturing process.

In the filing’s own words

A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.

What exactly they claim (claim 1)

1. A method for simulating a layout of an integrated circuit manufactured by a semiconductor process, the method comprising: extracting a plurality of pattern layouts from layout data that defines the layout; generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process; generating sample data by sampling the training data; generating feature data including a three-dimensional array from the sample data; providing the sample data and the feature data to a simulator and a machine learning model, respectively; and training the machine learning model based on an output of the machine learning model and an output of the simulator.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Method and system for simulating and verifying layout based on distribution
Patent number
US12743571B2
Application number
18151051
Filed
Jan 6, 2023
Granted
Sep 22, 2026
Inventors
8
Claims
20

Classified under

G06F 30/392 Physics & computingG06F 30/398 Physics & computingG06F 2119/02 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.