Samsung patents memory circuit that fixes signal timing errors
Samsung has been granted a patent for a specific circuit design used in memory systems. The invention uses built-in feedback loops to automatically adjust for small voltage differences and timing delays in the data signals.
In the filing’s own words
An input circuit includes a first input buffer connected to a corresponding data pin, a second input buffer connected to a data strobe pin, and a repeater configured to delay an output signal of the first input buffer, and further includes a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and a second loop configured to correct a delay offset of the repeater.
What exactly they claim (claim 1)
1. A memory system comprising: a buffer chip; a memory controller configured to transmit and receive a data strobe signal and a data signal to and from the buffer chip; and a plurality of non-volatile memory devices configured to transmit and receive the data strobe signal and the data signal to and from the buffer chip, each non-volatile memory device including a memory interface circuit comprising a plurality of data pins and a data strobe pin, each data pin connected to a corresponding data signal line, the data signal line configured to carry one of bit values for each bit position of the data signal, and the data strobe pin connected to a data strobe signal line configured to carry the data strobe signal, the memory interface circuit further including a plurality of input circuits, and each input circuit comprising a first input buffer connected to a corresponding data pin, a second input buffer connected to the data strobe pin, a repeater configured to delay an output signal of the first input buffer, a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and a second loop configured to correct a delay offset of the repeater.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Input circuit, memory interface circuit and memory system
- Patent number
- US12743371B2
- Application number
- 19014983
- Filed
- Jan 9, 2025
- Granted
- Sep 22, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06F 12/0246 Physics & computingG11C 16/32 Physics & computingG11C 16/0483 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.