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Samsung patents chip inspection method that finds light exposure errors

Samsung has patented a method for checking the precise width of tiny patterns on computer chips. The process involves exposing a light-sensitive coating to different amounts of light, etching the material, and measuring the resulting lines to identify if the light exposure was too high or too low.

Why it mattersThis improves the quality control of semiconductor manufacturing by helping engineers pinpoint exactly where the light exposure process went wrong during chip production.

In the filing’s own words

A method for inspecting a critical dimension may include providing a substrate, applying a photoresist on the substrate, variably irradiating a dose of light onto the photoresist, performing a photo process to develop the photoresist to form a photoresist pattern, performing an etching process using the photoresist pattern as an etching mask to form a plurality of patterns, measuring a width of each of the plurality of patterns and a spacing between adjacent ones of the plurality of patterns, and identifying a cause of a defect in the photo process based on the measured width and the measured spacing.

What exactly they claim (claim 1)

1. A method for inspecting a critical dimension, the method comprising: applying a photoresist on a substrate; variably irradiating a dose of light onto the photoresist; performing a photo process on the photoresist, the photo process including developing the photoresist to form a photoresist pattern; forming a plurality of patterns on the substrate, the forming the plurality of patterns including performing an etching process using the photoresist pattern as an etching mask; measuring a width of each of the plurality of patterns and a spacing between adjacent ones of the plurality of patterns to obtain a measured width and a measured spacing; and identifying a cause of a defect in the photo process based on the measured width and the measured spacing.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Critical dimension inspection method and semiconductor device manufacturing method using the same
Patent number
US12743026B2
Application number
18302375
Filed
Apr 18, 2023
Granted
Sep 22, 2026
Inventors
3
Claims
20

Classified under

G03F 7/70625 Physics & computingG03F 7/0025 Physics & computingG03F 7/0392 Physics & computingG03F 7/2002 Physics & computingG03F 7/70466 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.