Samsung patents chip package with capacitors and power pins on the bottom edge

1. A semiconductor package, comprising: a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region; a first semiconductor chip on an upper surface of the first structure; a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure; a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip, the first ball array being directly adjacent to first sidewalls of the passive element in a first horizontal direction and directly adjacent to second sidewalls of the passive element in a second horizontal direction, respectively, the second horizontal direction being perpendicular to the first horizontal direction; a first conductive pad in the passive element region on the lower surface of the first structure, the first conductive pad connecting the first structure and the passive element to each other, the first conductive pad grounding the passive element; and a second conductive pad in the passive element region on the lower surface of the first structure, the second conductive pad connecting the first structure and the passive element to each other, the second conductive pad being spaced apart from the first conductive pad in the first horizontal direction, the second conductive pad electrically connecting the passive element and the first power solder balls to each other, wherein the passive element is a capacitor.