Samsung patents chip stack design with vertical wiring holes
This filing describes a semiconductor package where multiple chips are stacked vertically on a base. The design uses small holes, called penetration vias, that run through the chips to allow electrical connections to pass from the bottom to the top layers.
In the filing’s own words
A semiconductor package may include a chip stack, a first semiconductor chip provided on a top surface of the chip stack, outer terminals provided on a bottom surface of the chip stack, and a mold layer provided on a bottom surface of the first semiconductor chip to enclose the chip stack. The chip stack may include a second semiconductor chip including first penetration vias, which are provided in second semiconductor chip and are exposed to an outside of the second semiconductor chip. The chip stack may include third semiconductor chips stacked on a top surface of the second semiconductor chip. Each of the third semiconductor chips may include second penetration vias, which are provided to penetrate the same and are exposed to an outside of the same. The first semiconductor chip may have a width larger than the chip stack, and the first semiconductor chip may include a logic chip.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a package substrate; a chip stack; a first semiconductor chip on a top surface of the chip stack; outer terminals on a bottom surface of the chip stack; and a mold layer on a bottom surface of the first semiconductor chip and enclosing the chip stack, wherein the chip stack comprises; a second semiconductor chip comprising first penetration vias, the first penetration vias penetrating the second semiconductor chip, the first penetration vias exposed to an outside of the second semiconductor chip from a bottom surface thereof, and third semiconductor chips stacked on a top surface of the second semiconductor chip, and wherein each of the third semiconductor chips comprises second penetration vias penetrating therethrough and exposed to an outside thereof from a bottom surface thereof, a width of the first semiconductor chip is larger than a width of each of the third semiconductor chips and larger than a width of the second semiconductor chip, the second semiconductor chip is a bottommost chip between the package substrate and the first semiconductor chip, and the first semiconductor chip comprises a logic chip.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package
- Patent number
- US12740491B2
- Application number
- 18608030
- Filed
- Mar 18, 2024
- Granted
- Sep 15, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 90/28 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 74/111 Electricity & electronicsH10W 90/297 Electricity & electronicsH10W 90/722 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.