Samsung patents stacked chip package with dummy posts for stability
This patent describes a method for building a semiconductor package by stacking two chips inside a frame. It uses specific 'dummy' posts and filling layers to secure the chips and ensure electrical connections are stable during manufacturing.
In the filing’s own words
A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor package, the method comprising: disposing a first semiconductor chip and a first bump pattern in a through-opening of a frame, the first bump pattern being on a first active surface of the first semiconductor chip; forming a first filling layer filling a space between the first semiconductor chip and side surfaces of the frame defining the through-opening; forming a mask layer having via holes on the frame and the first filling layer; forming a first lower post and a first dummy post in the via holes, the first lower post being on the first bump pattern, and the first dummy post being on the frame; disposing a second semiconductor chip and a second bump pattern on the first semiconductor chip, the second bump pattern being on a second active surface of the second semiconductor chip; and forming a second filling layer covering the first filling layer, the first lower post, the first dummy post, the second semiconductor chip and the second bump pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package
- Patent number
- US12740488B2
- Application number
- 18675679
- Filed
- May 28, 2024
- Granted
- Sep 15, 2026
- Inventors
- 2
- Claims
- 19
Classified under
H10W 90/00 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 76/161 Electricity & electronicsH10W 72/07252 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.