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Samsung patents chip stacking method that bonds protective layers together

Samsung describes a way to stack two semiconductor chips vertically by directly bonding their protective coating layers. This method connects the chips' electrical pads while sealing the structure without needing extra glue or solder between the main bodies.

Why it mattersThis technique helps manufacturers build denser computer components by simplifying how chips are stacked, which is a standard part of making modern processors more compact.

In the filing’s own words

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.

What exactly they claim (claim 1)

1. A semiconductor package, comprising: a first semiconductor chip; and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes a first substrate, a plurality of through electrodes that penetrate the first substrate, a first wiring layer on a front side surface of the first substrate, first bonding pads on the first wiring layer and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first wiring layer, and a first passivation layer on the first wiring layer and that exposes at least portions of the first bonding pads and the first test pad, wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer; wherein the second semiconductor chip includes a second substrate, a second wiring layer on a front side surface of the second substrate, third bonding pads on the second wiring layer, a second test pad on the second wiring layer, and a second passivation layer on the second wiring layer and that exposes at least portions of the third bonding pads and the second test pad, wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and wherein the first passivation layer and the second passivation layer are directly bonded to each other.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor package and method of manufacturing the semiconductor package
Patent number
US12740485B2
Application number
18359031
Filed
Jul 26, 2023
Granted
Sep 15, 2026
Inventors
3
Claims
20

Classified under

H10W 90/00 Electricity & electronicsH10P 74/273 Electricity & electronicsH10W 72/923 Electricity & electronicsH10W 72/926 Electricity & electronicsH10W 72/934 Electricity & electronicsH10W 72/936 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.