Samsung patents chip package design that stacks memory on three sides
This patent describes a method for arranging computer chips on a central board called an interposer. It places two main chip stacks on opposite sides and a third stack on the side, all connected through buffer chips to manage data flow.
In the filing’s own words
A semiconductor package includes: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first and second buffer chips on the interposer; a first chip stack adjacent to the first side of the interposer and connected to the first buffer chip; a second chip stack adjacent to the second side of the interposer and connected to the second buffer chip; a third chip stack adjacent to the third side of the interposer, and wherein the third chip stack includes first and second groups of semiconductor chips, which are electrically connected to the first and second buffer chips, respectively, via the interconnect circuit.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first buffer chip on the interposer; a second buffer chip on the interposer, wherein the second buffer chip is spaced apart from the first buffer chip; a first chip stack on the substrate, wherein the first chip stack is adjacent to the first side of the interposer and electrically connected to the first buffer chip; a second chip stack on the substrate, wherein the second chip stack is adjacent to the second side of the interposer and electrically connected to the second buffer chip; a third chip stack on the substrate, wherein the third chip stack is adjacent to the third side of the interposer, and wherein the third chip stack includes a first group of semiconductor chips, which is electrically connected to the first buffer chip via the interconnect circuit of the interposer, and a second group of semiconductor chips, which is electrically connected to the second buffer chip via the interconnect circuit of the interposer; an encapsulant on the interposer, the first chip stack, the second chip stack, and the third chip stack; and connection bumps on the substrate and electrically connected to the wiring circuit.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package
- Patent number
- US12740482B2
- Application number
- 18308358
- Filed
- Apr 27, 2023
- Granted
- Sep 15, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 90/401 Electricity & electronicsH10W 90/701 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.