Samsung patents 3D memory chip using ferroelectric layers
Samsung describes a vertical memory structure where a special material called a ferroelectric layer sits between the control wire and the storage channel. This design allows the chip to store data in a 3D stack, potentially improving how information is packed and accessed.
In the filing’s own words
A semiconductor device may include first conductive lines spaced apart from each other in a first direction on a substrate, second conductive lines spaced apart from the first conductive lines in a second direction, a gate electrode between the first and second conductive lines and extending in the first direction, a first selection gate electrode between the first conductive lines and the gate electrode and extending in the first direction, a plurality of channel patterns surrounding a side surface of the gate electrode and spaced apart from each other in the first direction, a plurality of first selection channel patterns surrounding a side surface of the first selection gate electrode and a ferroelectric pattern between the gate electrode and each of the channel patterns. The first selection channel patterns may be spaced apart from each other in the first direction and connected to the channel patterns, respectively.
What exactly they claim (claim 1)
1. A semiconductor device comprising: first conductive lines on a substrate and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the substrate; second conductive lines spaced apart from the first conductive lines in a second direction, the second direction being parallel to the upper surface of the substrate; a gate electrode between the first conductive lines and the second conductive lines, the gate electrode extending in the first direction; a first selection gate electrode between the first conductive lines and the gate electrode, the first selection gate electrode extending in the first direction; a plurality of channel patterns surrounding a side surface of the gate electrode, the plurality of channel patterns being spaced apart from each other in the first direction; a plurality of first selection channel patterns surrounding a side surface of the first selection gate electrode, and spaced apart from each other in the first direction, the plurality of first selection channel patterns connected to the plurality of channel patterns, respectively; and a ferroelectric pattern between the gate electrode and each of the plurality of channel patterns, wherein the first conductive lines are electrically connected to the plurality of first selection channel patterns, respectively, and each of the plurality of channel patterns is electrically connected to a corresponding second conductive line among the second conductive lines.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device
- Patent number
- US12740400B2
- Application number
- 18457907
- Filed
- Aug 29, 2023
- Granted
- Sep 15, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10B 51/10 Electricity & electronicsH10B 51/20 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 64/033 Electricity & electronicsH10D 64/689 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.